1. Field of the Invention
The present invention relates to a multiport memory in which a write port and a read port can independently access to memory cells and, more specifically, to a multiport memory in which 1 bit can correspond to a plurality of columns of a memory cell array.
2. Description of the Background Art
As the semiconductor technique has been developed recently, dual port memories having two inlets of data have been developed in the field of memories. In a dual port memory, master and slave CPUs share one memory to access the same. The master CPU has priority, and the slave CPU accesses the memory when the master CPU is not accessing the memory.
As a further improvement of the dual port memory, multiport memories have been developed in which two or more CPUs can independently access to a common memory. Generally, the dual port memories are also called as multiport memories.
FIG. 25 is a block diagram of a multiport memory having one write port and one read port.
Referring to the figure, the multiport memory has a M words.times.N bits structure, wherein either M or N is determined as a power of 2. A memory cell 1 stores 1 bit of data. A memory cell array is formed by arranging the memory cells 1 in M rows.times.N columns. A write address decoder 2a drives write word lines WW0, WW1, . . . WWM - 1 to "1" or "0" in response to an externally applied write address WA. The write word lines are arranged in the row direction in the memory cell array.
A read address decoder 2b drives read word lines RW0, RW1, . . . RWM - 1 to "1" or "0" in response to an externally applied address RA. The read word lines RW0, RW1, . . . RWM - 1 are arranged in the row direction in the memory cell array, and the write word lines WW0, WW1, . . . WWM - 1 and the read word lines are arranged alternately.
A data input circuit 3 drives write bit lines WB0, WB1, . . . WBN - 1 to "1" or "0" in response to externally input data DI0, DI1, . . . DIN - 1. The write bit lines WB0, WB1, . . . WBN - 1 are arranged in the column direction in the memory cell array.
Sense amplifiers 4 are connected to the read bit lines RB0, RB1, . . . RBN - 1 for detecting and amplifying data stored in the memory cells 1 to externally output N bits of data DO0, DO1, . . . DON - 1.
In the following, the write word lines WW0, WW1, . . . WWN - 1, the read word lines RW0, RW1, . . . RWN - 1, the write bit lines WB0, WB1, . . . WBN - 1 and the read bit lines RB0, RB1, . . . RBN - 1 are referred to as WWi, RWi, WBj and RWj (where i=1, 2, . . . N - 1, j=1, 2, . . . N - 1). A write port comprises a write address WA, write word lines WWi, write bit lines WBj, input data DI, a data input circuit 3 and a write address decoder 2a. A read port comprises a read address RA, read word lines RWi, read bit lines RBj, output data DO, a read address decoder 2b and sense amplifiers 4.
FIG. 26 is a detailed circuit diagram of the memory cell 1. The reference characters WW, RW, WB and RB represent arbitrary write word line, read word line, write bit line and read bit line, respectively.
Referring to the figure, the memory cell 1 comprises a write access gate 6, a memory circuit 5 and a read access gate 7. The write access gate 6 has its gate electrode connected to a write word line WW, its drain electrode connected to a write bit line WB and its source electrode connected to the memory circuit 5. The memory circuit 5 comprises a flipflop circuit, an inverter 5c, a write terminal A and an output terminal B, and the flipflop circuit includes inverters 5a and 5b whose output terminals and input terminals are connected to each other. The write terminal A is connected to the source electrode of the access gate 6, and the output terminal B is connected to the inverter 5c. An output terminal (read terminal C) of the inverter 5c is connected to a drain electrode of a read access gate 7. The read access gate 7 has its source electrode connected to the read bit line RB and its gate electrode connected to the read word line RW.
FIG. 27 shows a 2-input 4-output decoder included in each of the address decoders 2a and 2b. Referring to the figure, when 1 bit address is applied through the address lines RA0 and RA1, respectively, the decoder drives one of the write word lines WW0, WW1, WW2 and WW3 to "1" and others to "0". This address decoder is used singly in a multiport memory of 4 words.times.4 bits as shown in FIG. 30.
FIG. 28 show the data input circuit. Referring to the figure, externally input data DI is set to a prescribed voltage by two stages of inverters to be fed to the write bit line WB.
FIG. 29 (a) shows the sense amplifier 4. The sense amplifier 4 rises the voltage of the data applied from the memory cell 1 through the read bit line RB to a prescribed value by a pull up gate 4a, amplifies the same by inverters 4b and 4c and outputs data DO externally. Other than the circuit shown in FIG. 29 (a), a current detecting type circuit such as shown in FIG. 29 (b) may be used as the sense amplifier.
The operation of the above described conventional multiport memory will be described.
[I] Data writing operation
A word to be written out of M words is designated by an address WA. The write address decoder 2a decodes the designated address WA, sets one of the write word lines WWi to "1" and sets other word lines to "0". The access gate 6 of the memory cell connected to the word line WWi which is set at "1" is rendered conductive, so that the write bit line WBj is electrically connected to the write terminal A. The data DIj to be written is externally applied to the data input circuit 3, and the data input circuit 3 drives the write bit line WBj to "1" or "0" in response to the value of the data DIj. Consequently, if the write access gate 6 is rendered conductive, the value of the write terminal A attains to a value corresponding to DIj, that is, the value driven by the data input circuit 3, regardless of the values of the write terminal A and of the output terminal B of the memory circuit 5.
By the above described operation, writing to the memory cell 1 connected to the write word line WWi is completed. After completion of writing, when the write word line WW1 is set to "0", the write bit line WBj is electrically cut from the write terminal A, and the value written in the flipflop circuit is maintained. Therefore, as long as the write word line WWi is "0", new data cannot be written even if data is input to the write bit line WBj.
[II] Data reading
Reading of data is carried out by the read port. The word to be read out of M words is designated by an external read address RA, the read address decoder 2b decodes the read address RA to set the corresponding one of the read word lines RWi to "1" and set other read word lines to "0". The read access gate 7 of the memory cell 1 connected to the read word line RWi set at "1" is rendered conductive, so that the read terminal C of the memory circuit 5 is electrically connected with the read bit line RBj. Therefore, the value of the read bit line RBj is driven to the value of the read terminal C of the memory circuit 5. Thus the data stored in the memory cell 1 connected to the read word line RWi set at "1" is applied to the sense amplifier 4. The sense amplifier 4 detects and amplifies the applied data, and externally outputs N bits of data DO0, DO1, . . . DON - 1.
In the above described conventional multiport memory, when the write word line WWi is set to "1", the data applied from the data input 3 are written to all the memory cells connected to the write word line which is set to "1". Namely, data is written to the memory cells of all columns corresponding to one row of the memory cell array. Therefore one row must correspond to one word, and one column must correspond to one bit, and accordingly an independent bit line must be arranged column by column. Therefore, the ratio of length (M).times.width (N) of the memory cell cannot be changed.
Namely, the ratio of length.times.width is unchangeable, so that the degree of free design is limited when it is connected to other circuits or when it is integrated in combination with other circuits.